1. Field of the Invention
The present invention relates to hardware for priority processing in a communication device interchanging information in hardware which is employed for packet communication or the like, and more particularly, it relates to a buffer control memory which is employed in a digital communication device interchanging information in ATM (asynchronous transfer mode) hardware or the like.
2. Background of the Invention
FIG. 25 is a conceptual diagram for illustrating an ATM system which is described in "An ATM Switching System Based on a Distributed Control Architecture" by T. Koinuma et al., 1990 International Switching Symposium, May 27th-June 1st, Stockholm, Sweden, for example.
Referring to FIG. 25, numeral 1 denotes an ATM network which is formed by an OAM (operation, administration and maintenance) network, an intelligent network and a transmission network, numeral 2 denotes ATM switching units for forming the transmission network of the ATM network 1, and numeral 3 denotes user network interfaces (hereinafter referred to as UNIs) for connecting devices of users with the ATM network 1. Numeral 4 denotes a local area network of a user which is connected with the ATM network 1 by the UNI 3, numeral 5 denotes multimedia work stations of users which are connected with the ATM network 1 by the UNIs 3, numeral 6 denotes a video conference of a user which is connected with the ATM network 1 by the UNI 3, numeral 7 denotes units for assembling/disassembling cells, numeral 8 denotes existent networks such as N-ISDN which are connected with the ATM network 1 through the units 7, and numeral 9 denotes a private network which is connected with the ATM network 1 through the unit 7.
In general, there are requirements for making various communication operations through the ATM network 1. Namely, there are requirements for interconnection between the LAN 4 and other LANs, bulk file transfer between the multimedia work stations 5 each other, and the video conference 6 with combination of picture and sound data through the ATM network 1. Thus, the ATM network 1 is extremely dispersed in holding times of such communication operations, communication information generation characteristics (traffic characteristics) and the like.
In the ATM network 1, all data are carried on the transmission network through fixed length packets called cells. Each cell is formed by a header part and an information field part, and the header part stores an identifier indicating the destination. Each ATM switching unit 2 identifies the destination through the identifier which is stored in the header part, to transfer each cell. The OAM network is adapted to transmit information for maintaining/controlling the ATM network 1. In general, the OAM network is formed by a virtual network for transmitting information by OAM cells which are transmitted on the transmission network of the ATM network 1.
In order to implement a basic ATM switching function, each ATM switching unit 2 comprises a cell interconnection module (hereinafter referred to as CIM) 10 for controlling large flow of cells between the module and a line, a cell switching module (hereinafter referred to as CSM) 11 for making multiplex communication through a cell transmission hierarchy which is different from that of the CIM 10 and the like, for example.
FIG. 26 illustrates an exemplary CIM 10. The CIM 10 shown in FIG. 26 performs three-stage switching operations, and is provided therein with four first switching elements 12 receiving cells from other CSMs 11, four second switching elements 13 receiving the cells from the first switching elements 12, and four third switching elements 14 receiving the cells from the second switching elements 12 and transmitting the same to other CSMs 11. Each switching unit has 4 by 4 ports. Thus, each CIM 10 switches 64 links in each hierarchy.
A plurality of ATM cells which are transmitted on the ATM network 1 shown in FIG. 25 are stored in each switching unit. Each ATM switching unit sorts the respective ATM cells to the destinations thereof, so that the ATM cells are finally successively outputted from the CIM 10 to outgoing lines corresponding to the destinations. The cells are inputted from the CSMs 11 in the first switching elements 12 and outputted from the third switching elements 14 to the CSMs 11 at a fixed transmission speed of about 155 Mb/s, for example. The cells are transmitted between the first switching elements 12 and the second switching elements 13 as well as between the second switching elements 13 and the third switching elements 14 at variable transmission speeds of not more than 620 Mb/s.
FIG. 27 illustrates the structure of each ATM switching element, which is a principal part forming the ATM switching unit 2. Referring to FIG. 27, numeral 21 denotes four input interface blocks which are connected to an input line 20, numeral 22 denotes a common buffer and control block, and numeral 23 denotes four output interface blocks which are connected to an outgoing line 24.
Each input interface block 21 comprises a receiving interface 21a, a filter 21b for selecting cell data, a FIFO buffer 21c for storing the cell data, and an input/write control part 21d for controlling the receiving interface 21a, the filter 21b and the FIFO buffer 21c. Each input interface block 21 receives the cell data in a 4-bit parallel manner.
The common buffer and control block 22 comprises 31 buffers, a write arbiter 22b, a read arbiter 22c and an empty buffer queue 22d. This common buffer and control block 22 receives write requests and the cell data from the input interface blocks 21, to store the cell data in buffers having buffer numbers stored in the empty buffer queue 22d.
Each output interface block 23 comprises a FIFO buffer 23a, a transmission interface 23b, a read/output control part 23c for controlling the FIFO buffer 23a and the transmission interface 23b, and an output queue 23d for storing buffer numbers storing outputted cell data. The output queue 23d is provided in correspondence to an output port. Since the cell data have destination data, the output queue 23d corresponding to the port for outputting written cell data is supplied with the buffer numbers in which the cell data are written from the input/write control part 21d. Each output interface block 23 supplies the numbers of the buffers from which the data are read to the empty buffer queue 22d after the cell data are outputted.
The cells arriving at the ATM switching unit 2 are switched by the ATM switching elements 12, 13 and 14, and transmitted to outgoing lines corresponding to data of the destinations held by the cells.
Description is now made on the structure of another ATM switching element. FIGS. 28 to 31 show the structure and the operation of an ATM switching element which is described in "A High-Speed CMOS Circuit for 1.2 Gb/s 16.times.16 ATM Switching" by Alain Chemarin et al., IEEE Journal of Solid-State Circuits, Vol. 27, July 1992, for example.
FIG. 28 is a block diagram showing the structure of the ATM switching element. Referring to FIG. 28, numeral 25 denotes 16 receiving control blocks which are provided in correspondence to 16 inputs, numeral 26 denotes seven ATM switching parts which are provided by processing 28 divided input signals every four bits, numeral 27 denotes transmission control blocks for assembling the 28 divided output signals outputted from the ATM switching parts 26 for allowing transmission and outputting the same, numeral 28 denotes a header processing part for processing the headers of the respective cells as received, and numeral 29 denotes a control circuit part for generating write addresses and read addresses corresponding to processing results received from the header processing part 28. Extra headers are further added to heads of the header parts of the cell data as inputted, for controlling processing performed in the ATM switching unit.
FIG. 29 is a block diagram showing the structure of each ATM switching element 26 shown in FIG. 28. Referring to FIG. 29, numeral 30 denotes incoming rotating matrix block for serial-to-parallel converting the cell data as inputted, numeral 31 denotes a memory device which is divided into 16 banks for storing the cell data, numeral 32 denotes outgoing rotating matrix block for parallel-to-serial converting the cell data to original forms, numeral 33 denotes delaying block for delaying the write addresses for processing the header parts, numeral 34 denotes write address registers having shift register structures for supplying the write addresses for making the cell data stored in the memory device 31, numeral 35 denotes read address registers having shift register structures for supplying read addresses for reading the cell data from the memory device 31, and numeral 36 denotes signaling block for indicating vacated addresses.
FIG. 30 is a block diagram for illustrating the structure of the control circuit part 29 shown in FIG. 28. Referring to FIG. 30, numeral 36 denotes address management block for outputting write addresses, numeral 37 denotes multicasting calculation block for transmitting a single inputted cell to a plurality of destinations, numeral 38 denotes 16 queues of FIFO structures which are provided in correspondence to outgoing lines for outputting read addresses, numeral 39 denotes a queue for indicating empty addresses capable of supplying write addresses to the address management block 36, numeral 40 denotes signalling insertion & extraction block for indicating addresses which may generate write addresses, and numeral 41 denotes control logic.
Since the queues 38 are in FIFO structures, the respective outgoing lines output the cell data in order of the addresses stored in the queues 38. In a multicasting operation of outputting the same cell data on a plurality of outgoing lines, the multicasting calculation block 37 copies the queues 38 and hence the plurality of queues 38 corresponding to different outgoing lines output the same read addresses respectively. Thus, it is possible to transmit a single ATM cell which is inputted in the ATM switching unit to a plurality of outgoing lines.
FIG. 31 illustrates the flow of the cell data. Referring to FIG. 31, numerals identical to those in FIG. 30 denote the same elements. In the flow shown in FIG. 31, the cell data inputted in an input J are transmitted from an output N, while those inputted from an input I are multicasted and transmitted from outputs L and N.
The ATM network 1 shown in FIG. 25 is controlled by the OAM network etc. so that the ATM cells arrive at the destinations within a prescribed time. In order to hold a video conference through the ATM network 1, for example, it is necessary to transmit information with minimum delay, even if the quality of the information is deteriorated. In order to transfer data between work stations, on the other hand, the quality of the information comes into question in relation to errors or the like while the transmission speed for the information may be regarded as less important. Further, the ATM network 1 may temporarily burst until such data over the transmission quantity of the ATM network 1. In the ATM network 1, therefore, it is necessary to control the stay times of cells in the ATM switching unit 2 etc. in response to the information contents, communication situation or the like, depending on the busy condition of the ATM network 1.
Generally known is a method of controlling the information stay times by introducing a concept of delay priority for a request for making cells arrive at destinations within a prescribed time and separately controlling calls requiring immediate processing and allowing a certain degree of delay respectively. For example, an apparatus allowing delay priority is shown in NTT R & D, No. 3, Vol. 42, 1993, p. 412, FIG. 7. This apparatus carries out bilevel priority control through a first priority buffer and a second priority buffer.
In a conventional network for packet communication such as the ATM network having the aforementioned structure, the cells are outputted in order of arrival in the switching system such as the ATM switching unit 2, for example, and hence the cells passing through the ATM switching unit 2 may not arrive at the destinations within a prescribed time.
Even if the concept of delay priority is introduced, this problem cannot be sufficiently solved since a determination is made only as to priority and no control is made on arrival times of priority cells and non-priority cells.